1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and, more particularly, to a structure of a contact portion for taking out a conductive layer pattern of a diffusion layer, a wiring layer, etc. located at a deep position of the semiconductor device and a method of manufacturing the same.
2. Description of the Related Arts
A conventional method of manufacturing a so-called capacitor-over-bit-line (COB) type dynamic random access memory (hereinafter referred to as a "DRAM") will be explained with reference to FIG. 1.
As shown in (1) of FIG. 1, a lower layer of the inter-layer insulating film 21 is formed on a semiconductor substrate 10 on which a diffusion layer 12 of a transistor 11 of a DRAM cell is formed. Then, a doped polysilicon film 31 is deposited on this lower layer of the inter-layer insulating film 21 to a thickness of a few hundreds nanometers, then an aperture 32 is formed in the doped polysilicon film 31 above the diffusion layer 12 by lithography and etching using the mask pattern of the connection hole. Then, a polysilicon side wall 33 is formed on the side wall of the opening 32 by an ordinary side wall forming technique. Subsequently, a first connection hole 22 is formed in the lower layer of the inter-layer insulating film 21 by anisotropic etching using the doped polysilicon film 31 and the polysilicon side wall 32 as a mask.
Next, the doped polysilicon film 31 and the polysilicon side wall 32 are removed, then, as shown in (2) of FIG. 1, polysilicon is filled in the first connection hole 22 to form a plug 23 acting as the contact with the diffusion layer 12.
Next, a conductive layer is formed on the lower layer inter-layer insulating film 21 and the conductive layer is patterned by lithography and etching, thereby to form a pad 24 connected to the first plug 23 and having a larger diameter than that of the first connection hole 22.
Subsequently, as shown in (3) of FIG. 1, an upper layer inter-layer insulating film 25 covering the pad 24 is formed on the lower layer of the inter-layer insulating film 21. Then, the same method as that for forming the first connection hole 22 is used to form a second connection hole 26 in the upper layer of the inter-layer insulating film on the pad 24. Next, this second connection hole 26 is filled and, at the same time, a conductive portion 27 is formed on the upper layer of the inter-layer insulating film 25. Next, the conductive portion 27 is patterned by lithography and etching. Then, a storage node contact 28 is formed by the conductive portion 27 inside the second connection hole 26. Part of the storage node 29 is formed by the conductive portion on the upper layer of the inter-layer insulating film 25.
Note that, though not illustrated, it is also possible to form the upper layer of the inter-layer insulating film 25 after forming the pad 24 so as to eliminate the step difference due to the thickness of the pad 24 and then perform the step of forming the insulating film and the step for flattening the insulating film.
Next, a plan view of the COP type DRAM cell will be shown in FIG. 2. Gate electrodes 51a to 51d of selection transistors 56a to 56g are arranged in parallel. Bit lines 53a to 53c connected to the diffusion layers of these selection transistors 56a to 56g by bit contacts 52 are arranged orthogonal to the gate electrodes 51a to 51d. The diffusion layers of the selection transistors 56a to 56g are provided with node contacts 54a to 54d connected to (not illustrated) capacitors. A sectional view taken along a line A-A' of the figure is given in FIG. 3. and a sectional view taken along a line B-B' of the figure is given in FIG. 17. As seen from these sectional views, the node contacts 54a to 54d are "middle takeout contacts" using "pad-equipped" plugs. This DRAM is a COB type in which a bit line is a buried in the inter-layer insulating film between a selection transistor STr and a capacitor CAP. Further, the sectional view of FIG. 17 shows also a DRAM cell portion and a partial peripheral circuit.
Next, a simple explanation will be made of the method of manufacture of the COB type DRAM cell shown in FIG. 17 of a second related art by referring to FIG. 4 to FIG. 17. First, as shown in FIG. 4, an element isolation oxide film 120 is formed on a P type silicon substrate in which an N well and a P well are formed so to perform element isolation, then a (not illustrated) gate insulating film is formed by a thermal oxidation method, polysilicon 131a and tungsten silicide 131b are laminated, then patterning is carried out to form a gate electrode 131. Ion implantation is carried out by using this gate electrode 131 as a mask to form a lightly doped drain (LDD) 101.
Next, as shown in FIG. 5, a thin silicon oxide film 152 is formed for an etching stopper on the entire surface. Then, polysilicon is deposited, then etched back to form a side wall 132 constituted by polysilicon on a side wall of the gate electrode. Then, ion implantation is carried out by using this side wall 132 as a mask to form a source and drain region 112.
The side wall 132 is removed, then, as shown in FIG. 6, a silicon nitride film 153 is formed for an etching stopper on the entire surface by low pressure chemical vapor deposition (CVD). After this, a natural silicate glass (NSG) film 204 is formed by O.sub.3 -tetraethoxysilane (TEOS), then a boro-phospho-silicate-glass (BPSG) film 152 is formed by O.sub.3 -TEOS.
Next, as shown in FIG. 7, the BPSG 155 is made to flow to flatten it. Next, polysilicon 133 is deposited, then resist patterning R11 for making apertures for the bit contacts and node contacts.
Next, as shown in FIG. 8, the polysilicon film 133, the BPSG film 155, and the NSG film 154 are etched and the etching is stopped midway to form a preparatory contact hole, then polysilicon is deposited, then etched back so as to form a side wall 134 constituted by polysilicon on the side wall of this preparatory contact hole. Next, etching is performed by using this side wall 134 and the polysilicon film 133 as a mask so as to open a contact hole reaching the substrate and open a shrunken bit line contact hole BCH and a node contact hole NCH.
After opening the contact holes, as shown in FIG. 9, a polysilicon film 135 is deposited to fill the contact holes BCH and NCH.
Next, as shown in FIG. 10, the polysilicon films 135 and 133 and the side wall 134 are etched back to make the surface of the polysilicon film 135 (including also the side wall 134) lower than the preparatory contact hole. By this, in each contact, a so-called pad-equipped polyplug 136 for middle takeout is formed.
Next, as shown in FIG. 11, the BPSG film 155 is etched to level its surface with that of the polyplug 136, then a silicon oxide film 157 is formed by LP-TEOS and a silicon nitride film 158 by a low pressure CVD process on the entire surface. A resist R12 is formed and patterned for the contact openings for forming bit lines.
Next, as shown in FIG. 12, the silicon nitride film 158 and the silicon oxide film 159 are etched by using the resist film R12 as a mask to expose the plug surface of the bit line contact. The resist film R12 is then removed, then a polysilicon film 138 for forming the bit lines and a tungsten suicide 139 are deposited, the resist pattern for the bit lines is formed, and the etching is carried out using this as a mask to pattern the bit lines BL. Next, a silicon oxide film 160 is thinly formed by LP-TEOS and a silicon nitride film 161 by the low pressure CVD process, then an NSG film 162 and BPSG 163 are deposited and the BPSG 163 is made to flow to flatten it.
Next, as shown in FIG. 13, the surface is shaved by etching etc. to flatten it, then a silicon nitride film 164 is deposited acting as an etching stopper at the time of formation of the capacitor. A polysilicon film 140 is deposited on this, then the resist R13 is formed and patterned for opening contacts for the node contact plugs.
Next, as shown in FIG. 14, this is etched using the resist R13 as a mark to form a preparatory contact hole in the polysilicon film 140. Next, polysilicon is deposited, then is etched back to form a side wall 141 constituted by polysilicon on the side wall of the preparatory contact hole, then the silicon nitride film 164, BPSG film 163, NSG film 162, silicon nitride film 158, and silicon oxide film 157 are successively etched by using the side wall 141 and the polysilicon film 140 as the mask to open a shrunken node contact hole reaching the pad, then a polysilicon 312 is deposited to fill the contact hole.
Next, as shown in FIG. 15, the polysilicon film 142, the polysilicon film 140, and the side wall 141 are etched back to remove the polysilicon film while leaving the polyplug 144, then a polysilicon film 145 is deposited for the node electrode. On this, the silicon oxide film 165 for forming the cylinder type capacitor is deposited thickly and a resist film R14 formed with a pattern for the bottom wall electrode of the capacitor.
Next, as shown in FIG. 16, anisotropic etching is carried out by using the resist film R14 as a mask to pattern the silicon oxide film 165 and the polysilicon film 145, then the resist film R14 is removed. Next, a polysilicon film is deposited, then etched back to form a side wall 146 constituted by polysilicon at the side portion of the silicon oxide film. A cylinder type node electrode is formed by removing the silicon oxide 165 by wet etching. Next, an ONO film (structure in which silicon oxide is sandwiched by silicon nitride films) 106 is formed on the node electrode, then a polysilicon film 147 acting as a plate electrode is deposited, then the plate electrode 147 and the silicon nitride film 164 are patterned to form the plate electrode and form a capacitor CAP is formed. By this, a DRAM is completed.
Next, as shown in FIG. 17, an inter-layer insulating film 167 is deposited to bury the capacitor and is flattened, then a contact hole is opened for connecting the plate electrode, the peripheral circuit, and the wiring circuit. Then, a Ti/TiN film 148 is formed as a closely adhered layer covering the inner wall of the contact hole, then tungsten is deposited and then etched back to form a blanket tungsten 149. After this, a wiring layer 140 is patterned to obtain a COB type DRAM having a cross-sectional structure shown in FIG. 17.
In a COB type DRAM cell manufactured by the process of the related art, there are three wiring layers for the gate electrodes, bit lines, and capacitors and three inter-layer insulating films, therefore the height of the memory cell portion becomes about 1 .mu.m, the inter-layer insulating film of the peripheral circuit becomes thick, and the aspect ratio of the contacts of the peripheral circuit becomes large, therefore there is a problem in that the diameter of the contacts of the peripheral circuits cannot be made small and the degree of integration cannot be raised.